Semiconductor device and method of packaging a semiconductor device with a clip

ABSTRACT

A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

FIELD OF THE INVENTION

This invention relates generally to a semiconductor device and method ofpackaging of a leadless semiconductor device, and in one embodiment to asemiconductor device and method of packaging of a leadless semiconductordevice having a clip interconnect.

BACKGROUND

During packaging, semiconductor devices typically undergo a number ofprocessing steps to form the complete semiconductor device. Suchpackaging steps usually include leadframe etching and metal bumping forplacement of the semiconductor die placement. These steps are thentypically followed by a high temperature die bonding and then a wirebonding process for electrically interconnecting the semiconductordevice prior to the completing steps of molding, curing, dicing andcuring.

These conventional steps and the typical components used in thepackaging process contribute to the overall size and processing cost ofthe complete semiconductor device package. In particular during etchingand metal bumping of the leadframe significant cost and time is incurreddepending on the choice of leadframe and etching materials. Theresulting metal bump height also contributes to the overall thickness ofthe semiconductor device. In the die bonding step, the process must beconducted in high temperatures, usually in the range of 300° C. to 430°C., which also contributes to the overall cost in the packaging process.Additionally, exposing the semiconductor device to such high processingtemperatures during the package process may contribute to increasing therisk of processing imperfections of the complete semiconductor device.Wire bonding the die for providing electrical interconnects for thesemiconductor device typically requires sufficient clearance for thewires above the die and contributes to a significant portion of theoverall thickness of the semiconductor device package.

Attempts have been made to reduce the thickness of the die and limit theprocessing costs in the process steps of packaging semiconductordevices. However, such attempts have lead to other problems. Forexample, to reduce the overall thickness in conventional leadless designsemiconductor devices based on leadframe configurations, limiting thethickness of the die makes the die brittle and makes the die susceptibleto damage during die placement. Frequently, damage may include cracks inthe die and the like that can result from high compression impact of thedie on the leadframe during die placement. Additionally, the wireplacement and interconnections formed in the wire bonding process maylimit the electrical performance of the semiconductor device and may bea source of semiconductor device failure due to a faulty connection,wire misalignment or short. Such limitations or imperfections may make afinished leadless semiconductor device defective.

Therefore, there is a need for a method of packaging a semiconductordevice and a semiconductor device that overcomes or at least alleviatesthe problems associated with conventional packaging processes ofleadless semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that embodiments may be fully and more clearly understood byway of non-limitative examples, the following description is taken inconjunction with the accompanying drawings in which like referencenumerals designate similar or corresponding elements, regions andportions, and in which:

FIG. 1A-1J illustrates a cross-sectional view of a semiconductor deviceduring the process of packaging the semi-conductor device in accordancewith an embodiment of the invention;

FIG. 2A-2B illustrate a cross-sectional view (FIG. 2A) and topperspective view (FIG. 2B) of a clip connector in accordance with anembodiment.

FIG. 3A-3D illustrates the expended wafer concept of an embodiment ofthe invention with a plan view of an expended wafer showing die to diespacing of a plurality of dies (FIG. 3A), a top plan view of a sectionof FIG. 3A in more detail showing the clip interconnect placement on thedie tops (FIG. 3B), a the top plan view of FIG. 3B after wafer levelmolding (FIG. 3C), and a top cross-sectional view of FIG. 3C after wafersingulation in accordance with an embodiment.

FIG. 4A-4B illustrate a bottom plan view of the view of a semiconductordevice taken along line A-A of FIG. 4A (FIG. 4B), and a cross-sectionalview of the semiconductor device with a clip interconnect taken alongline B-B (FIG. 4C) in accordance with an embodiment.

FIG. 5A-5F illustrates the strip form concept of an embodiment of theinvention with a plan view of an wafer without foil expansion showingX-Y direction die pick up for strip form processing of a plurality ofdies (FIG. 5A), a top plan view of a section of FIG. 5A in more detailshowing the clip interconnect placement on the die tops (FIG. 5B), theprocess of conductive phase screen printing in cross-sectional view(FIG. 5C), a cross-sectional view of the clip interconnect afterprocessing illustrated in FIG. 5C (FIG. 5D), after molding (FIG. 5E),and after singulation (FIG. 5F) in accordance with an embodiment.

FIG. 6 is a flow chart illustrating a method of packaging a leadlesssemiconductor device having a clip interconnect in accordance with anembodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

One embodiment provides a method of manufacturing a semiconductordevice, including providing a chip, the chip having a first face and asecond face opposite to the first face; providing at least one cliphaving first contact region and a second contact region on a same faceof the at least one clip; attaching the first contact region of the atleast one clip to the first face of the chip; encapsulating the chip andthe at least one clip; and providing that the second contact region ofthe at least one clip is exposed after the encapsulation.

In one embodiment it is provided that the second face of the clip isexposed. The method may further comprise placing the second face of thechip onto the carrier. The second region of the at least one clip may beplaced onto the carrier. In encapsulating the chip and the at least onechip may include placing the chip and the at least one clip placed intoa molding unit. In encapsulating the chip and the at least one clip mayinclude placing the chip and the at least one clip into a molding unitwith the second face of the chip and the second region of the at leaston clip placed on the carrier. The second contact region of the at leastone clip is exposed may include keeping the second contact regionexposed while encapsulating the chip and the at least one clip. The atleast one clip may be mechanically biased so that the second regionpresses against the carrier after attachment of the first contact regionof the at least one clip to the first face of the chip.

In one embodiment the chip may include at least one of an integratedcircuit, a power transistor, a sensor, or the like. The chip may includea source contact of a transistor, or an emitter contact of a transistor,on the first face of the chip and a drain contact, or a collectorcontact, of the transistor on the second face of the chip. The firstregion of the at least one clip may be attached to the source contact,or the emitter contact, of the chip. The first region of a second one ofthe at least one of the clip may be attached to the gate or base of thechip.

In one embodiment, the first contact region of the at least one clip maybe attached to the first face of the chip by at least one of soldering,welding, conductive epoxy or the like. The clips may be made from ametal sheet. The thickness of the metal sheet may be between for example100 mm and 2000 mm depending on a particular application. Each of theclips is bent at least twice. The first contact region and the secondcontact region may be substantially coplanar. The clip may comprise aplurality of clips that are interconnected to form a clip interconnectmesh for a plurality of chips.

One embodiment provides a method for manufacturing multiplesemiconductor devices, including providing an array of chips placed on acarrier; providing an array of clips, the clips being physically ormechanically connected with each other and each providing for a firstcontact region and a second contact region on a same face of the clip;attaching the first contact regions of the clips to the chips so thatthe second contact regions touch the carrier; encapsulating the array ofchips and the array of clips; and disconnecting the connection betweenthe clips after encapsulation.

One embodiment provides a semiconductor device, including a chipdefining a first face, and a second face opposite to the first face; atleast one clip defining a first contact region and a second contactregion on a same face of the at least one clip, the first contact regionbeing attached to the first face of the chip and the second contactregion being located essentially within a same plane with the secondface of the clip.

One embodiment provides a clip interconnect for a semiconductor device,including at least one clip defining a first contact region and a secondcontact region on a same face of the at least one clip, the chipdefining a first face, and a second face opposite to the first face, thefirst contact region being attached to the first face of the chip andthe second contact region being located substantially within a sameplane with the second face of the clip.

A method of manufacturing a semiconductor device having a clipinterconnect is disclosed. FIG. 1A-1J illustrates a cross-sectional viewof a semiconductor device during the process of packaging thesemi-conductor device in accordance with an embodiment of the invention.FIG. 1A illustrates a die 12 having a die pad 14 affixed to a temporarysupport such as an adhesive tape or foil 24.

FIG. 1B illustrates fixing of a clip interconnect 10 to the die 12. Theclip interconnect is fixed to the die with a fixing means such as aconductive paste 16, which may be applied by epoxy screen print forexample. The clip interconnect 10 may have a first contact region 18 forelectrical contact with the conductive paste and the die. The clipinterconnect 10 may have a second contact region for being exposed onthe surface of the molding of the completed semiconductor packagedevice. FIG. 1C illustrates the clip interconnect bonded and fixed tothe die and adhered to the adhesive tape 24. The clip interconnect maybe pre-plated copper (Cu), nickel (Ni), palladium (Pd), gold (Au) andthe like.

The die and the clip interconnect are then molded with a moldingcompound 26, which may be powder molding, liquid molding or the like.The molding process may be performed with known techniques in theindustry. FIG. 1D illustrates the die 12 and the clip connectencapsulated in the mold material 26. FIG. 1D illustrates that themolding material is removed from the adhesive tape 24 after the adhesivetape is provided on a temporary carrier 22. FIG. 1E illustrates that thefirst surface of the mold material 30 and second side of the moldmaterial surface 28. The die pad 34 of the die 12 and the foot pin 32 ofthe clip interconnect 10 are exposed from the first surface 30 of themolding material 26. A lamination 36 is provided on the second surface28 of the mold material 26 as illustrated in FIG. 1F in order tocomplete the processing. The final stages of the processing areillustrated as saw area 38 is illustrated in FIG. 1G and testing withtesters 40 to check performance of the device is illustrated in FIG. 1H.Further processing such as radiators and UV lamps 42 is illustrated inFIG. 1I to fabricate the completed semiconductor device package 48having a chip first face 44 and a chip second face 46 as illustrated inFIG. 1J. The clip interconnect may act not only as an interconnect, butmay also act as input/output (I/O) lead or leads. For example the dieback metal of the die and the foot print are acting as I/Os.

FIG. 2A illustrates a cross-sectional view of the die and clipinterconnect to show the thickness of the semiconductor device package.The thickness achieved may be for example 0.2 mm. The thickness of thesemiconductor device package may be arranged for a specific application.For example the clearance between the top of the clip interconnect tothe surface of the mold material may only be approximately 50 μm forexample, and from top of clip interconnect to top of die may only beapproximately 100 μm for example. The overall thickness may only be forexample 200 μm. FIG. 2B illustrates top perspective view of a clipconnector in accordance with an embodiment of the invention. The clipconnector has a tip 52, a base 54, and a connecting portion 56 betweenthe tip and the base. Of course it will be appreciated that theconfiguration of the clip interconnect may be arranged with a differentshape and profile. The configuration of the clip interconnect may bearranged for a particular application chip design, or the like. A meshof clip interconnects may be configured and is described in furtherdetail with respect to FIGS. 3B and 5D. The adjacent clip interconnectsjoined by connectors. The connectors may be of the same or differentmaterial than the material of the clip interconnects. The mesh of clipinterconnects may be affixed to the plurality of dies with differentfixing means and processes. For example, conductive paste may be usedand applied by conductive paste screen printing. The conductive pastemay be at room temperature. Other means of fixing the mesh of clipinterconnects is possible, such as for example soldering, welding andthe like. The cycle processing time of such a clip interconnect mesh isimproved.

FIG. 3A-3D illustrates the expanded wafer concept of one embodiment ofthe invention. FIG. 3A illustrates a plan view 60 of an expended wafershowing die to die spacing of a plurality of dies 64 fixed on anadhesive tape or file 62. FIG. 3B illustrates a top plan view of asection 66 of FIG. 3A in more detail showing the clip interconnect mesh76 placement on the die tops 68. The clip interconnect mesh 76 comprisesconnectors 67,69 between the clip interconnects from tip to adjacentfoot print of adjacent clip interconnects and between the foot print toadjacent footprint of adjacent clip interconnects. FIG. 3C is across-sectional top view 72 of clip interconnect on top of die top ofafter wafer level molding with mold material 74. FIG. 3D illustrates atop plan view 80 of FIG. 3C after wafer singulation in accordance withan embodiment of the invention. The vertical singulation lines 82 andhorizontal singulation lines 84 are illustrated with gaps between thedies 86 and corresponding clip connect 88. In this expanded tape waferlevel concept, after singulation the expandable wafer tape, foil or thelike is expanded to create the desired die to die spacing for the meshclip interconnect and foot prints to be positioned on the empty die todie spacing area on the expanded adhesive tape.

The gaps are formed by expanding the adhesive tape or foil 62illustrated in FIG. 3A after singulation. The foil may be stretchedevenly to achieve the uniform gaps between the devices. Such a device tostretch the foil, tape adhesives or the like are known in the industryand is available, for example provided by Semiconductor EquipmentCorporation of California, United States of America. The expandablefoil, tape adhesives or the like may have high temperaturecharacteristics to withstand temperatures during processing such as 200°C.

FIG. 4A is a bottom plan view of the view 90 of a semiconductor devicein FIG. 3D showing the die bottom view and the clip interconnect bottomfoot print view. FIG. 4B is a cross-sectional view 96 of taken alongline A-A of a semiconductor device in FIG. 3D illustrating the die andclip interconnect encapsulated with mold material.

FIG. 5A-5F illustrates the strip form concept of an embodiment of theinvention. FIG. 5A illustrates a plan view of a wafer without foilexpansion showing X-Y direction 114,116 for row die pick up for stripform processing of a plurality of dies 102. For example a single row, ormore than one row, may be picked up in the X and Y directions to createempty rows on the wafer level foil. The dies are picked up and attachedto a support surface for further processing such as for example anadhesive tape, wafer or the like. FIG. 5B and FIG. 5C show in moredetail the processing with respect to a die 104 and clip interconnect110. The die is fixed or die bonded to the wafer substrate 106. The diebonding may be at room temperature. It will be appreciated that the diemay be fixed to thermal resistance tape. The conductive paste 108 isapplied to the die to fix the clip interconnect 110 to the die 104. Theplacement of the clip interconnect to the die of a single device 112 isillustrated in FIG. 5C, and the placement of the clip interconnect mesh121 comprising a plurality of clip interconnects 124 to the plurality ofdies 122 after conductive epoxy screen print is illustrated in thecross-sectional top view 120 in FIG. 5D. Similar views 126,130 areillustrated of the die and clip interconnect after molding in FIG. 5 Eand after singulation in FIG. 5F. It will be appreciated that FIG. 5D-5Fillustrate a strip form configuration of the tape foil, however, otherforms, shapes and configurations can be envisaged. In the wafer levelpackaging concept described, the individual die pick up and die attachedprocess is facilitated as conventional individual wire bondinginterconnect processing is not required.

FIG. 6 is a flow chart of a method 200 of packaging a leadlesssemiconductor device having a clip interconnect in accordance with oneembodiment. The method may be with a single die and single clipinterconnect or a plurality of clip interconnects formed in a mesh andaffixed to a plurality of dies. An expandable wafer with foil or tapewith a temporary carrier may be provided 202. The die is attached 204 tothe tape or foil. The conductive paste is applied 206 such as by screenprinting to the die and the clip interconnect or mesh of clipinterconnects is attached 208 to the die. Further processing 210,212,214such as molding curing and detaping and lamination, dicing and UVradiation, and dicing is performed to provide the completedsemiconductor device package. After singulation, the foil or adhesivetape may be stretched to provide the adequate gaps required for furtherprocessing. In configurations with fixed non-expandable foil or adhesivetape, the dies may be positioned by pick and place on the wafer oradhesive tape with processes known in the industry.

With the methods and configurations discussed, improved quality insemiconductor processing is achieved over conventional applicationsusing wafer back metal and Au bump. Process such as etch/Ni/Ag leadframeand high temperature die bonding and wire bonding are not necessary.Further procedures such as Cu-etching and Ni/Au deposition are similarlynot required. Even vision process of inspection of completedsemiconductor devices may be eliminated as quality is more certain withthe clip interconnect device discussed. As materials such as Cu may beused instead of Au wire typically selected for wire bonding, theelectrical performance is improved while costs may be minimized. Thethickness of the overall package height is reduced as wire clearance isnot required, the actual size of the die may be minimized, there is noleadframe Ni/Au bump height, and the like.

While embodiments of the invention have been described and illustrated,it will be understood by those skilled in the technology concerned thatmany variations or modifications in details of design or constructionmay be made without departing from the present invention.

The invention claimed is:
 1. A method of manufacturing a semiconductordevice, comprising: providing a chip, the chip having a first face and asecond face opposite to the first face; providing at least one cliphaving first contact region and a second contact region on a first faceof the at least one clip; attaching the first contact region of the atleast one clip to the first face of the chip; encapsulating the chip andthe at least one clip; and providing that the second contact region ofthe at least one clip is exposed after the encapsulation, wherein thesecond contact region is located substantially within a same plane witha die pad on the second face of the chip.
 2. The method of claim 1comprising providing that a second face of the at least one clip isexposed.
 3. The method of claim 1 comprising placing a second face ofthe chip onto a carrier.
 4. The method of claim 1 comprising placing thesecond contact region of the at least one clip onto a carrier.
 5. Themethod of claim 1 wherein encapsulating the chip and the at least oneclip includes placing the chip and the at least one clip placed into amolding unit.
 6. The method of claim 1 wherein encapsulating the chipand the at least one clip includes placing the chip and the at least oneclip into a molding unit with the second face of the chip and the secondregion of the at least one clip placed on a carrier.
 7. The method ofclaim 1 wherein providing that the second contact region of the at leastone clip is exposed includes keeping the second contact region exposedwhile encapsulating the chip and the at least one clip.
 8. The method ofclaim 1 wherein the at least one clip is mechanically biased so that thesecond region presses against a carrier after attachment of the firstcontact region of the at least one clip to the first face of the chip.9. The method of claim 1 wherein the chip comprises at least one of anintegrated circuit, a power transistor, or a sensor.
 10. The method ofclaim 1 wherein the chip comprises a source contact of a transistor, oran emitter contact of a transistor, on the first face of the chip, and adrain contact of a transistor, or a collector contact of the transistor,on the second face of the chip.
 11. The method of claim 1 wherein thefirst region of the at least one clip is attached to a source contact ofthe chip, or an emitter contact of the chip.
 12. The method of claim 1wherein the first region of a second one of the at least one of the clipis attached to a gate of the chip, or a base of the chip.
 13. The methodof claim 1 wherein the first contact region of the at least one clip isattached to the first face of the chip by at least one of soldering,welding and conductive epoxy.
 14. The method of claim 1 wherein the atleast one clip is made from a metal sheet.
 15. The method of claim 14wherein a thickness of the metal sheet is between 100 mm and 500 mm. 16.The method of claim 1 wherein the at least one clip is bent at leasttwice.
 17. The method of claim 1 wherein the first contact region andthe second contact region are essentially coplanar.
 18. The method ofclaim 1 wherein the at least one clip comprises a plurality of clipsthat are interconnected to form a clip interconnect mesh.
 19. A methodfor manufacturing multiple semiconductor devices, comprising: providingan array of chips placed on a carrier; providing an array of clips, theclips being physically connected with each other and each providing fora first contact region and an opposing second contact region on a sameface of the clip; attaching the first contact regions of at least one ofthe clips to each of the array of the chips so that the second contactregions of each of the respective clips touch the carrier; encapsulatingthe array of chips and the array of clips; and disconnecting theconnection between the clips attached to different chips afterencapsulation.
 20. The method of claim 19 further comprises stretchingthe carrier for increasing the distance between adjacent chips of thearray of chips.
 21. The method of claim 19 further comprisesencapsulating the chips and the clips.
 22. The method of claim 19wherein the first contact region and the second contact regions areessentially plane-parallel.